1. Field of the Invention
The present invention relates to a semiconductor memory device which has a ferroelectric capacitor. More particularly, the present invention relates to the technique for achieving uniform operation characteristics over the whole of a memory cell array region of the semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device which has a ferroelectric capacitor is conventionally known. An example of such a conventional semiconductor memory device will be described using a logic circuit embedded FeRAM (Ferroelectric Random Access Memory). FIG. 1 shows an example of the circuit layout of a macro of the logic circuit embedded FeRAM.
Referring to FIG. 1, the macro of the logic circuit embedded FeRAM has a plurality of memory cell arrays. Sense amplifiers are arranged to sandwich each memory cell array in a horizontal direction, and word line and plate line drivers are arranged to sandwich a set of the sense amplifiers and the memory cell arrays in a vertical direction. Moreover, an X decoder is arranged above the uppermost word line and plate line driver. A Y decoder is arranged on the left side of the sets of the sense amplifiers and the memory cell arrays. A space is provided between the memory cell array and the sense amplifier and between the memory cell array and the word line and plate line driver. The space is hereinafter called a xe2x80x9cconnection regionxe2x80x9d.
FIG. 2 shows a circuit diagram of FeRAM cells of the memory cell array. As shown in FIG. 2 as a unit cell of 2T2C, the FeRAM cell is comprised of two transistors and two ferroelectric capacitors. The FeRAM cell with the structure of 2T2C holds data by applying two voltages of different polarities to the ferroelectric capacitors. In case of reading the data, plate lines are biased from a ground voltage to a power supply voltage and the electric charge from the ferroelectric capacitor with the polarity inverted and the electric charge from the ferroelectric capacitor with the polarity non-inverted are outputted onto a pair of bit lines. Then, the voltage difference on the pair of bit lines is amplified by the sense amplifier and outputted outside.
FIG. 3 shows a cross sectional view of the conventional logic circuit embedded FeRAM formed as mentioned above. The logic circuit embedded FeRAM has a 3-layer wiring line structure. The logic circuit embedded FeRAM has a memory cell array region where the FeRAM cells are arranged, a peripheral circuit region where peripheral circuits such as the sense amplifier, the word line driver and the plate line driver are arranged, and a connection region formed between them.
In the memory cell array region, the ferroelectric capacitor is comprised of an upper electrode, a ferroelectric film and a lower electrode and is formed on an uppermost aluminum wiring line layer containing third metal wiring lines. In the connection region, a dummy capacitor shown by slanted lines is comprised of the upper electrode, the ferroelectric film and the lower electrode. The dummy capacitor functions to prevent 2-dimension effects such as proximity effect and pattern sparse dense effect in a lithography process or a dry etching process in the connection region so that the ferroelectric capacitors are formed to have a predetermined size over the whole of the memory cell array region.
By the way, the logic circuit embedded FeRAM has the ferroelectric capacitors on an aluminum wiring line layer, as described above, and a contact plug is comprised of tungsten. The aluminum wiring line layer is damaged when annealing is carried out in a high temperature (600xc2x0 C. to 750xc2x0 C.) to form the ferroelectric capacitor. Therefore, a crystal growth method is conventionally adopted to form the ferroelectric capacitor at a relatively low temperature. In this case, it is essential to form the ferroelectric capacitor at the growth temperature of 450xc2x0 C. or below to maintain the reliability of the contact plug and the aluminum wiring line. Generally, when the growth temperature of a PZT (Pb(ZrX,Ti1xe2x88x92X)O3) film as a ferroelectric film is lowered, the crystalline of the PZT film is degraded and the ferroelectric characteristics are degraded.
The characteristic 1 (solid line) in FIG. 4 shows the ferroelectric characteristics when the PZT film is formed at the growth temperature of 450xc2x0 C. In this case, the ferroelectric capacitor with large polarization can be formed. Also, the characteristic 2 (broken line) shows the ferroelectric characteristics when the PZT film is formed at the growth temperature of 430xc2x0 C. In the case, the ferroelectric capacitor with small polarization is formed.
FIG. 5 is a diagram showing the bit line voltage difference of all the FeRAM cells of a test memory cell array which contains the cells for voltage measurement. In FIG. 5, the bit line voltage difference from 0 V to about 1.3 V is shown in a sparse dense manner of dots. A part of a darker color shows a larger bit line voltage difference. Each of the FeRAM cells has the PZT film manufactured at the growth temperature of 430xc2x0 C. The FeRAM cell has a larger bit line voltage difference or a larger operation margin when the bit line voltage difference is larger. Referring to FIG. 5, the operation margin of the FeRAM cell is large in a right end section and in the center section and the operation margin of the FeRAM cell is small in an upper end section and a lower end section. The operation margin depends on the characteristics of the ferroelectric capacitor, as shown in FIG. 4. That is, the operation margin is large when the polarization is large like the characteristic 1, and the operation margin is small when the polarization is small like the characteristic 2.
The deviation in the operation margin depending on the physical position of the FeRAM cell results from the difference in the characteristics of the FeRAM cells, as shown in FIG. 5. It could be considered that the deviation is based on the surface temperature of the lower electrode, which is generally comprised of platinum (Pt), of the ferroelectric capacitor when the PZT film is formed.
In conjunction with the above description, a semiconductor memory device is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 4-168765). In this reference, the memory device is comprised of a memory cell array region where a plurality of memory cells are formed, each of which is comprised of a memory transistor and a capacitor, and a peripheral circuit region where a plurality of peripheral circuit transistors are formed. The memory device is formed on a semiconductor substrate. A set of gate electrode films is arranged in parallel in the memory cell array region to have a predetermined space. Thus, using the gate electrodes, memory transistors are formed. A set of gate electrode films is arranged in parallel in the peripheral circuit region to have a predetermined space. Thus, using the gate electrodes, peripheral circuit transistors are formed. Dummy wiring lines are also formed in the peripheral circuit region. The space between the gate electrodes films in the memory cell array region is substantially the same as the space between the gate electrodes films or between the gate electrode and the dummy wiring line in the memory cell array region.
Also, a semiconductor device is disclosed in is disclosed in Japanese Laid Open Patent Application (JP-A-Heisei 11-74482). In the reference, a plurality of semiconductor devices are formed on a semiconductor substrate in a memory cell region to have conductive films piled via insulating films. A dummy pattern has at least a conductive film and is formed on a position closer to the peripheral transistor region than any one of the semiconductor devices. An interlayer insulating film covers the semiconductor devices and the dummy pattern and has an inclined portion between the memory cell region and the peripheral transistor region. A part of the dummy pattern is exposed from the interlayer insulating film.
Therefore, an object of the present invention is to provide a semiconductor memory device and a manufacturing method, in which memory cells with large operation margins can be formed over the whole of a memory cell array region.
In an aspect of the present invention, a method of manufacturing a semiconductor memory device is achieved by (a) forming a lower electrode film on a semiconductor substrate via an interlayer insulating film; by (b) forming a ferroelectric film on the lower electrode layer while heating the lower electrode layer; by (c) forming an upper electrode film on the ferroelectric film; and by (d) forming ferroelectric capacitors in a memory cell array region, each of the ferroelectric capacitors comprising the lower electrode film, the ferroelectric film and the upper electrode film.
Here, it is desirable that the lower electrode film is formed of material containing at least one of platinum, iridium, iridium oxide, ruthenium and ruthenium oxide.
Also, the method may further comprise the step of (e) forming thermally conductive routes in the memory cell array region and a connection region outside the memory cell array region to pass through the interlayer insulating film to the semiconductor substrate, and to be connected with the lower electrode film. The lower electrode film is heated via the thermally conductive routes. In this case, it is desirable that contact plugs for the routes passing through a portion of the interlayer insulating film are formed each time the interlayer insulating film portion is formed. Also, the heating may be achieved by heating the semiconductor substrate.
Also, it is desirable that a density of the thermally conductive routes in the memory cell array region is substantially the same as that of the thermally conductive routes in the connection region
Also, additional thermally conductive routes may be formed in the interlayer insulating film in a peripheral circuit region outside the connection region to be connected with the thermally conductive routes in the connection region.
Also, the (b) forming step may desirably include heating the semiconductor substrate to about 450xc2x0 C.
Also, the (a) forming step may be achieved by forming the lower electrode film to extend outside the memory cell array region.
In another aspect of the present invention, a semiconductor memory device having a memory cell array region, a peripheral circuit region and a connection region between the memory cell array region and the peripheral circuit region, includes ferroelectric capacitors formed on a semiconductor substrate via an interlayer insulating film in the memory cell array region; and conductive films formed on the interlayer insulating film in the connection region. The conductive films are connected with the semiconductor substrate via conductive routes passing through the interlayer insulating film, respectively.
Here, a layer for the conductive films may be formed when a lower electrode layer for the ferroelectric capacitors is formed. In this case, the lower electrode layer may be formed of material containing at least one of platinum, iridium, iridium oxide, ruthenium and ruthenium oxide.
Also, the semiconductor memory device may further include MOS transistors formed on the semiconductor substrate in the memory cell array region and the connection region. Each of the ferroelectric capacitors may be connected with one of the MOS transistors formed in the memory cell array region and each of the conductive films may be connected with one of the MOS transistors formed in the connection region.
Also, it is desirable that a density of the ferroelectric capacitors is substantially the same as that of the conductive films.
Also, the semiconductor memory device may further include additional conductive films formed in the peripheral circuit region. The additional conductive films may be connected with any of the conductive routes in the connection region.
The semiconductor memory device may be a logic circuit embedded FeRAM, or a logic circuit embedded non-volatile SRAM.
In another aspect of the present invention, a method of manufacturing a semiconductor memory device, may be achieved by (a) forming MOS transistors in a memory cell array region and a connection region outside the memory cell array region, wherein a density of the MOS transistors in the memory cell array region is substantially the same as that of the MOS transistors in the connection region; by (b) forming an interlayer insulating film to cover the MOS transistors while forming thermally conductive routes, each of which extends from one of the MOS transistors to pass through the interlayer insulating film; by (c) forming a lower electrode film on a semiconductor substrate via the interlayer insulating film to be connected with the thermally conductive routes; by (d) forming a ferroelectric film on the lower electrode layer while heating the lower electrode layer; by (e) forming an upper electrode film on the ferroelectric film; and by (f) forming ferroelectric capacitors in the memory cell array region, each of the ferroelectric capacitors comprising the lower electrode film, the ferroelectric film and the upper electrode film.
In another aspect of the present invention, a method of manufacturing a semiconductor memory device, may be achieved by (a) forming MOS transistors in a memory cell array region and a connection region outside the memory cell array region, wherein a density of the MOS transistors in the memory cell array region is substantially the same as that of the MOS transistors in the connection region; by (b) forming an interlayer insulating film to cover the MOS transistors while forming thermally conductive routes, each of which extends from one of the MOS transistors to pass through the interlayer insulating film; by (c) forming a lower electrode film on a semiconductor substrate via the interlayer insulating film to be connected with the thermally conductive routes; by (d) forming a ferroelectric film on the lower electrode layer while heating the lower electrode layer via the thermally conductive routes; by (e) forming an upper electrode film on the ferroelectric film; and by (f) forming ferroelectric capacitors in the memory cell array region, each of the ferroelectric capacitors comprising the lower electrode film, the ferroelectric film and the upper electrode film.
Here, the (b) forming step further may be achieved by forming additional thermally conductive routes in the interlayer insulating film in a peripheral circuit region outside the connection region to be connected with the thermally conductive routes in the connection region.